The present invention relates to a multiplying digital-to-analog converter (MDAC), and more particularly, to a high-speed low supply voltage MDAC.
In the field of analog-to-digital converter (ADC), a pipeline ADC is commonly employed in high speed and high-resolution analog-to-digital converting operations. One of the most important blocks in the pipeline ADC is the MDAC (Multiplying digital-to-analog converter). Conventionally, there are a plurality of MDACs in the pipeline ADC, and each MDAC is responsible for generating a residue for use in the MDAC in next stage. Furthermore, the MDAC normally consists of an operational amplifier, a capacitor block, and a switching block, wherein the capacitor block is utilized to sample an input signal for assisting the switching block, and the operational amplifier outputs the residue between the input signal and an output bit of a subADC of the pipeline ADC to the next MDAC.
According to prior art, the common mode voltages of the input signal and the output signal of the operational amplifier are set to VDD/2, wherein VDD is the supply voltage of the operational amplifier. In addition, each switch in the switching block consists of an NMOS transistor MN combined with a PMOS transistor MP as shown in FIG. 1. FIG. 1 is a diagram illustrating a switch 10 according to prior art. When the MDAC operates under a low supply voltage, such as VDD=1.2V, a dead-zone emerges at the switch 10 when the switch is in the on mode. Please refer to FIG. 2. FIG. 2 is a diagram illustrating a relationship between the input voltage VIN and transconductance G of the NMOS transistor MN and the PMOS transistor of the switch 10 in the on mode. A curve 11 represents the transconductance G of the NMOS transistor, while a curve 12 represents the transconductance G of the PMOS transistor. It can be seen in the diagram that a dead-zone appears when the input voltage VIN is located between a voltage VDD-VTN and a voltage |VTP|, wherein VTN is a threshold voltage of the NMOS transistor and |VTP| is the absolute threshold voltage of the PMOS transistor. In other words, the switch 10 has the dead zone if the supply voltage VDD is low. If this is the case, the capacitor block may not be able to sample the input signal correctly.
Since the common mode voltages of the input signal of the operational amplifier are set to VDD/2, the input stage of the operational amplifier should also be biased at VDD/2. It is very difficult, however, to design an input stage biased at VDD/2 when the VDD is the low supply voltage but the system still needs to operate at high speed. Therefore, designing a pipeline ADC that operates under a low supply voltage but at a high operating speed is a current challenge in the field.